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Microprocessor Design with Dynamic Clock Source and Multi-Width Instructions

Keyu Chen, Xuyi Hu, Robert Killey

Submitted on 8 November 2022, last revised on 28 November 2022

Abstract

This paper introduces a novel 32-bit microprocessor, based on the RISC-V instruction set architecture, is designed,utilising a dynamic clock source to achieve high efficiency, overcoming the limitations of hardware delays. In addition, the microprocessor is also aimed to operate with both base (32-bit) instructions and 16-bit compressed instructions. The testing of the design is carried out using ModelSim with an ideal result.

Preprint

Subjects: Computer Science - Hardware Architecture; Electrical Engineering and Systems Science - Systems and Control

URL: http://arxiv.org/abs/2211.04455